1. Field of the Invention
The present invention relates generally to the protection of a vertical deflection integrated circuit (IC) for a monitor, and in particular to a device for protecting a vertical deflection IC for a monitor employing a dedicated display data channel (DDC) chip which can prevent the vertical deflection IC from getting damage due to an instantaneous supply of a vertical sync signal of 25 KHz or more to a vertical deflection circuit of the monitor when data stored in the dedicated DDC chip is read out by a computer.
2. Description of the Prior Art
Generally, a monitor may employ a dedicated DDC chip in which information on the specification, manufacturing date, serial number, etc. of the monitor has been stored by a manufacturer. If necessary, such DDC information can be displayed on the screen of the monitor by a user.
FIG. 1 is a block diagram of a conventional device for a monitor employing a dedicated DDC chip. Referring to FIG. 1, the conventional device is provided with a computer input/output (I/O) section 100 which outputs a vertical sync signal provided from a computer to a DDC section 110 and a vertical deflection section 120 when power is supplied, and then receives monitor information data from the DDC section 110 when a predetermined time elapses thereafter; a DDC section 110 which receives the vertical sync signal outputted from the computer I/O section 100, and then outputs the monitor information data stored therein to the computer I/O section 100 when the predetermined time elapses thereafter; and a vertical deflection section 120 which receives the vertical sync signal outputted from the computer I/O section 100 and performs vertical deflection in accordance with the input vertical sync signal.
The operation of the conventional device for a monitor employing the DDC chip will be described in detail.
When the power is supplied to the monitor, the computer I/O section 100 outputs a vertical sync signal of about 50-100 Hz as shown in FIG. 2A through its output terminal VO to the seventh pin P7 of the dedicated DDC chip 111 in the DDC section 110 and to the vertical deflection section 120.
The period during which ten pulses of the vertical sync signal are outputted corresponds to a waiting time for data transmission as shown in FIG. 2B. When this waiting time elapses, the DDC section 110 outputs the monitor information data stored in the dedicated DDC chip 111 through its fifth pin P5 to the data input terminal DI of the computer I/O section 100.
At this time, the monitor information data is transmitted with a data transmission frequency of about 25 KHz or more in order to shorten the data transmission time. In other words, the vertical sync signal of about 25 KHz or more is outputted from the output terminal VO of the computer I/O section 110 to the vertical deflection section 120, and thus the vertical deflection IC (not illustrated) in the vertical deflection section 120 performs vertical deflection in accordance with the vertical sync signal. As a result, the information stored in the dedicated DDC chip 111 in the DDC section 110 is displayed on the screen of the monitor.
After the data transmission as described above is completed, the computer I/O section 100 outputs the normal vertical sync signal of about 50-100 Hz through its output terminal VO to the seventh pin P7 of the dedicated DDC chip 111 in the DDC section 110 and to the vertical deflection section 120, resulting in that a normal image is displayed on the monitor screen.
In the conventional device for a monitor employing a dedicated DDC chip, however, the vertical deflection IC in the vertical deflection section 120 is designed to operate with a vertical sync signal of about 50-100 Hz, and thus it is liable to be damaged in the event that the vertical sync signal of about 25 KHz is inputted thereto for the transmission of the DDC data, thereby deteriorating the reliability of the monitor.